Method for Reading an EEPROM and Corresponding Device

ABSTRACT

One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.

This application claims priority to French Patent Application No.1560515, filed on Nov. 3, 2015, which application is hereby incorporatedherein by reference.

TECHNICAL FIELD

Various embodiments of the invention relate to memories, in particularnon-volatile memories of the electrically erasable and programmable type(EEPROM).

BACKGROUND

In EEPROM memories, the logical value of a bit is stored in a memorycell, comprising a state transistor and a selection transistor.

The state transistor is generally a floating-gate transistor, comprisinga control gate and a floating gate, and the information is expressed asa function of the charge on the floating gate. Typically, a negativecharge on the floating gate corresponds to a state referred to as“erased” (the logical value of the bit stored is, for example, “0”),whereas as positive charge on the floating gate corresponds to a statereferred to as “programmed” (the logical value of the stored bit is, forexample, “1”).

Generally speaking, the selection transistor allows the access to thestate transistor to be controlled. Its source is connected to the drainof the state transistor, and the source of the state transistor isconnected to a source line.

SUMMARY

One embodiment provides a method for reading a memory cell of a memoryplane of a memory of the erasable electrically-programmable ROM type.The word line and of the bit line to which the memory cell belongs areselected and the content of the cell is read via a read amplifier. Oneinput of the read amplifier is connected to the bit line and pre-chargedat a pre-charge voltage. During the read operation, a source voltagehigher than the pre-charge voltage is applied to the source of thefloating-gate transistor of the cell. A read current flows from the celltowards the input of the read amplifier and then flows through aprogrammed cell.

A memory device of the erasable electrically-programmable ROM typecomprises a memory plane of memory cells. A read circuit comprises aread amplifier, one input of which is configured so as to be pre-chargedat a pre-charge voltage. A controller is configured to select a wordline and a bit line to which a cell belongs, so as to read the contentof the cell via the read amplifier whose input is connected to theselected bit line. The controller is configured to apply a sourcevoltage that is higher than the pre-charge voltage to the source of thefloating-gate transistor of the cell. A read current flows from the celltowards the input of the read amplifier and then flows through aprogrammed cell.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent uponexamining the detailed description of non-limiting embodiments and theappended drawings in which:

FIG. 1 illustrates one pattern of the structure of a memory plane of amemory of the EEPROM type; and

FIGS. 2 and 3 show various embodiments of a device according to theinvention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A plurality memory cells can be distributed as a matrix in a memoryplane. One periodic pattern of a memory plane is shown in FIG. 1. Inthis case, the memory cells are non-volatile memories of theelectrically erasable and programmable type (EEPROM).

The access to a given memory cell CELij is achieved by virtue of adecoding of the memory plane PM. Each gate of the selection transistorsTS is connected to a word line WLi which runs in the X direction of thememory plane, and each drain of the selection transistors TS isconnected to a bit line BLj which runs in the Y direction of the memoryplane.

The source lines SL are generally parallel to the word lines WLi.

Generally speaking, the bit lines are grouped into columns eachcomprising M bit lines.

The memory cells of the same word line connected to the M bit lines of acolumn then form a memory word allowing M bits to be stored.

The control gates of the state transistors TGF of the memory cells of amemory word, situated in a given column at the intersection with the rowi, are controlled by the same control signal CGi, as shown in FIG. 1.

Thus, in order to read a data value stored by a memory cell, an input ofa read amplifier is pre-charged at a pre-charge voltage. Then, aconventional decoding of the memory plane is carried out in such amanner as to select the memory cell.

The bit line is then pre-charged to the same voltage level as that ofthe input of the read amplifier, typically around 1V.

The pre-charge is halted and the decoded cell (selected) can be read bymeans of the read amplifier. The source line is at ground.

An erased cell does not allow the current to flow and the bit lineremains at the pre-charged potential.

A programmed cell is conducting and allows the current to flow, whichtends to make the voltage on the bit line drop.

The variation of the voltage is subsequently converted by the readamplifier into a logical value corresponding to the logical value of thebit stored in the selected memory cell.

There exists a constant need to increase the quantity of memory cells ofa memory plane, in particular by reduction of the surface area occupiedby a memory cell.

For reduced lengths, current leaks (referenced 1 and 2 in FIG. 1) in theselection and non-selected state transistors can occur notably becauseof a “short-channel effect”. This is because a lowering of the potentialbarrier between the drain and the source takes place due to theextension of the space-charge region which comes close to the source, aneffect which is more marked the shorter the channels. This barrierlowering results in the current leaks.

This effect leads to current flowing from the bit line towards thesource line, usually connected to ground, through the non-selectedmemory cells.

The leaks associated with short-channel effects in the state transistorslead to instabilities in the read currents of the selected cells.

The leaks associated with short channel effects in the selectiontransistors mean that the bit-line current is equal to the read currentof the selected cell, increased by the leakage currents of the selectiontransistors of non-selected cells, placed in series with theircorresponding state transistors. These leakage currents therefore dependon the logical state of the non-selected cells, hence are unpredictable.The reduction in the size of the memory cells in the Y direction is thuslimited by the appearance of the current leaks associated withshort-channel effects in the state transistors and the selectiontransistors.

On the other hand, the selection transistors of neighboring bit linesmay have source and drain regions that are close, forming structures ofthe N/P/N type, typically isolated by shallow isolation trenches.

For reduced dimensions, it is then possible for current leaks 3, 4 tobypass the isolation trenches.

The current of the bit line is then also modified and can lead to readerrors.

The reduction in the size of the memory cells in the X direction is thuslimited by the appearance of current leaks 3, 4 between neighboring bitlines.

The current solutions with regard to read methods for reducing thecurrent leaks do not allow the leaks associated with short-channeleffects in the state and selection transistors to be prevented, and theydo not handle well the leaks from one bit line to another.

According to one embodiment, a method is provided for reading a memorycell of the EEPROM type aiming to eliminate as far as possible thepotential current leaks by short-channel effect in the state andselection transistors of the memory cells, together with the potentialcurrent leaks by diffusion of electrons between neighboring bit lines.

Thus, the method according to this embodiment notably allows memorycells with smaller dimensions to be formed and thus to increase thestructural compactness of the memory planes of the memories of theEEPROM type.

According to one aspect, a method is provided for reading a memory cellof a memory plane of a memory of the erasable electrically-programmableROM type, comprising a selection of the word line and of the bit line towhich the memory cell belongs, and a reading of the content of the cellvia a read amplifier, one input of which is connected to the bit lineand pre-charged at a pre-charge voltage.

According to a general feature of this aspect, during the readoperation, a source voltage higher than the pre-charge voltage isapplied to the source of the floating-gate transistor of the cell, aread current flowing from the cell towards the input of the readamplifier then flowing through a programmed cell.

In other words, for a programmed cell, hence conducting, the readcurrent flows in the opposite direction with respect to the prior art.

The potential barrier between the N/P/N junctions of the cells situatedon neighbouring bit lines is increased by virtue of the reverse biasingof the source. The transfer of electrons is then virtually impossibleand the leakage currents can be reduced by several orders of magnitude.

The memory cell can comprise a selection transistor whose source isconnected to the drain of the floating-gate transistor, whose gate isconnected to the word line and whose drain is connected to the input ofthe read amplifier via an auxiliary transistor configured for selectingthe bit line, the substrates of the selection transistor and of thefloating-gate transistor being connected to ground.

Thus, the voltage applied to the branches from which the leaks originateis always positive, and a “substrate effect” appears.

The substrate effect leads to a reduction in the leaks by increasing thepotential barrier between source and drain of a transistor and betweentwo closely-spaced bit lines.

According to one embodiment, and in the case of reading an erased cell,the voltage present at the input of the read amplifier is prevented fromgoing below the pre-charge voltage.

It is indeed advantageous to keep the voltage at the input of the readamplifier positive in order to reduce, or even eliminate, the currentleaks, in particular in the case of reading an erased cell, which hasthe tendency to make the voltage on the bit line drop.

The potential of the drain of an erased cell is the lowest potentialapplied to a diffusion N in the memory plane. If it is strictlypositive, then all the diffusions N in the memory plane are at astrictly positive potential and the current leaks are consequentlygreatly reduced by substrate effect.

According to one embodiment, the pre-charge voltage is equal to athreshold voltage of an MOS transistor, the source voltage then beinghigher than the threshold voltage of an MOS transistor.

According to another aspect of the invention, a memory device of theerasable electrically-programmable ROM type, comprising a memory planeof memory cells, a read circuit comprising a read amplifier, one inputof which is configured so as to be pre-charged at a pre-charge voltage,and a controller configured for selecting a word line and a bit line towhich a cell belongs, so as to read the content of the cell through theread amplifier whose input is connected to the selected bit line.

According to a general feature of this other aspect, the controller isconfigured to apply to the source of the floating-gate transistor of thecell a source voltage higher than the pre-charge voltage, a read currentflowing from the cell towards the input of the read amplifier then flowsthrough a programmed cell.

The cell can comprise a selection transistor whose source is connectedto the drain of the floating-gate transistor, whose gate is connected tothe word line and whose drain is connected to the input of the readamplifier via an auxiliary transistor configured for selecting the bitline, the substrates of the selection transistor and of thefloating-gate transistor being connected to ground.

The read amplifier is advantageously configured for drawing a currentfrom the drain of the selection transistor to ground, this tending tomake the drain voltage of the selection transistor of an erased celltend towards 0. The pre-charge is then aimed at preventing this voltagefrom falling below a certain minimum value in order to provide thesubstrate effect.

In other words, according to one embodiment, the read amplifier isconfigured for preventing the voltage present at the input of the readamplifier from falling below the pre-charge voltage, in the case ofreading an erased cell.

The read amplifier can be configured so that the pre-charge voltage isequal to a threshold voltage of an MOS transistor.

According to one embodiment, the read amplifier comprises a feedbackloop containing a first MOS transistor in common source configurationwhose drain is connected to the input of a second MOS transistor insource follower configuration, whose source is connected to the gate ofthe first MOS transistor and to the input of the read amplifier; thefeedback loop is thus configured to prevent the voltage present at theinput of the read amplifier from falling below the pre-charge voltage,which is moreover equal to the threshold voltage of the first MOStransistor.

The bit line is connected to the source of the transistor in sourcefollower configuration.

The read amplifier comprises a current source imposing a current toground on the pre-charge loop/bit-line assembly.

The various aspects and embodiments of the invention allow memory cellsto be read while greatly reducing the current leaks, rendering possiblea decrease in the surface area of the memory cells and thus animplementation of memory planes that are more compact than the currentimplementations.

FIG. 2 illustrates a memory device DIS of the EEPROM type according toone embodiment of the invention. Elements that are not needed for thedescription and for the understanding of the invention have purposelynot been shown.

The device DIS comprises a memory plane PM of memory cells CEL, with astructure similar to the structure described by FIG. 1, notablycomprising bit lines BL and word lines WL.

A controller MCOM, comprising row decoders DECX and column decodersDECY, manages the access to the memory cells CEL by selecting thecorresponding bit line BL and word line WL.

Thus, a selected cell is connected via a node BUSR to read circuit MLEC,notably to the input of a read amplifier AMPL whose output delivers alogical value DAT corresponding to the logical value of the bit storedin the selected memory cell.

FIG. 3 shows, more precisely, one example of the various circuits inFIG. 2, in particular the read amplifier AMPL.

A cell CEL of a memory plane PM comprising a selection transistor MN5and a floating-gate state transistor MN6 is notably shown.

A bit line BL is connected to the drain of the selection transistor MN5,a word line WL is connected to the gate of the selection transistor MN5,a control line CG is connected to the control gate of the statetransistor MN6 and a source line SL is connected to the source of thestate transistor MN6.

The substrates of the selection transistor MN5 and state transistor MN6are connected to ground.

A transistor MN4 controlled on its gate by a signal COL connects the bitline BL to an input node BUSR of the read amplifier AMPL.

The transistor MN4 is an element of the controller MCOM allowing a bitline of the memory plane to be selected, as a function of the signal COLproduced by the controller MCOM.

The read amplifier AMPL here comprises an output stage OUT and afeedback loop BCL connected to the input node BUSR of the read amplifierAMPL.

The feedback loop BCL notably comprises a first MOS transistor of the Ntype MN1 and a second MOS transistor of the N type MN2.

The source of the transistor MN1 is connected to ground, the drain ofthe transistor MN1 is connected to a current generator Iref1 via a nodeN1, and the gate of the transistor MN1 is connected to the input nodeBUSR of the amplifier AMPL. The current Iref1 is generated in such amanner as to be positive incoming into the drain of the transistor MN1.

The gate of the transistor MN2 is connected to the node N1, the drain ofthe transistor MN2 is connected to a stable positive voltage source Vdd,and the source of the transistor MN2 is connected to a stable currentsource Iref3 and to the input node BUSR. The current Iref3 is generatedin such a manner as to be positive outgoing from the source of thetransistor MN2.

In other words, the transistor MN1 is configured in common source modeand its drain is connected to the gate of the transistor MN2 configuredin source follower mode, the source of the transistor MN2 being fed backonto the gate of the transistor MN1.

The bit line is connected, via the transistor MN4, to the input of theread amplifier.

Furthermore, a transistor MN3 controlled by a signal SB is connected tothe node N1 and to ground.

The output stage OUT comprises an MOS transistor of the N type MN7 whosegate is connected to the node N1. The source of the transistor MN7 isconnected to ground and its drain to a current generator Iref2 via anode N2. The current Iref2 is generated in such a manner as to bepositive incoming onto the node N2.

The input of two inverters Inv1 and Inv2 in series is connected to thenode N2 and the output of the inverters forms the output of the readamplifier AMPL, delivering the signal DAT.

Furthermore, a transistor of the P type MP1, controlled by a signal RDis connected to a stable positive voltage source Vdd and to the node N2.

The signals SB and RD are generated by the read circuit MLEC.

During a wait phase, the read amplifier is inactive, the voltage of theinput node BUSR is floating, and the current sources are turned off.

The signal RD is at “0”, so that the input of the inverters in series isforced to Vdd and is not therefore floating, the output signal DAT thenbeing equal to “1”.

The signal SB is at “1”, so that the feedback loop BCL is“short-circuited” in order for the voltage of the input node BUSR of theamplifier AMPL to be floating, with the aim of limiting the powerconsumption.

The read phase is preceded by a pre-charge phase, during which the readamplifier is active and pre-charges the node BUSR to a pre-chargevoltage.

When the bit line BL is not selected, the current source Iref3 appliedto the node BUSR tends to make the voltage of the node BUSR fall belowthe threshold voltage of the transistor MN1.

The transistor MN1 is turned off, the voltage on the node N1 increasesby the action of the current source Iref1 connected to a stable positivevoltage source Vdd.

The transistor MN7 is then turned on but the voltage at the node N2 isheld at Vdd by the conducting transistor MP1.

The source follower configuration of the transistor MN2 transmits anincreasing voltage over the node BUSR until it reaches the thresholdvoltage of the transistor MN1, then making the voltage of the node N1decrease. As a consequence, the voltage transmitted over the node BUSRby the source follower configuration of the transistor MN2 decreases inthe same way until it reaches a stable situation.

This mechanism of the feedback loop BLC is stabilized when the voltageat the node BUSR is at the threshold voltage of the transistor MN1.

The pre-charge voltage therefore has the value of the threshold voltageof the transistor MN1, for example, substantially equal to 800 mV.

The controller MCOM selects the bit line BL by rendering the transistorMN4 conducting via a positive voltage COL, and the selected bit line isalso pre-charged at the pre-charge voltage.

The signal RD is at “0” and DAT is still equal to “1”.

During the read phase, the controller MCOM conventionally selects amemory cell by applying a positive voltage to the word line WL and bymaintaining the transistor MN4 in the conducting state.

A voltage higher than the pre-charge voltage, for example, substantiallyequal to 1.4V, is applied to the source lines SL, and a positivereference potential is applied to the control gate CG.

Advantageously, the reference potential applied to the control gate CGis such that a virgin cell, in other words not carrying any charge inthe floating gate of the state transistor, would deliver a voltage onthe bit line equal to the pre-charge voltage if this reference voltagewere applied to the control gate of its state transistor.

The reference voltage may, for example, be equal to 1.9V, but may alsobe equal to the voltage applied to the source line SL.

The current sources of the read amplifier AMPL are kept active, and thesignals RD and SB are respectively equal to “1” and “0”. The voltage atthe node N2 is then generated by the voltage source Vdd via the currentsource Iref2 and depends on the conducting or non-conducting state ofthe transistor MN7.

The current source Iref3 imposes a current to ground on thepre-charge/bit-line feedback loop assembly. The bit line BL indeed needsto be pulled down to ground in order to be able to test the conductionstate of the memory cell.

A memory cell in the erased state is non-conducting.

The mechanism of the feedback loop BCL previously described will bringthe voltage of the node BUSR back to the level of the pre-chargevoltage.

The voltage of the node N1 will increase in the course of this mechanismand render the transistor MN7 conducting, making the voltage of the nodeN2 drop. The signal DAT then goes to “0”.

A memory cell in the programmed state is conducting and will transmitthe voltage of the source line SL to the bit line BL and thus make thevoltage of the node BUSR increase significantly. The transistor MN1 willbe highly conducting, and will make the voltage at the node N1 drop andturn the transistor MN7 off.

The voltage of the node N2 then increases under the effect of thevoltage source Vdd via the current source Iref2 and the signal DAT thengoes to “1”.

In this embodiment, the read operation is carried out by detection of avariation in voltage, but it may notably be envisaged to detect avariation in current.

In the read phase, a read current flows from the memory cell towards theinput node BUSR of the read amplifier AMPL, and this read current cannotbe higher than the current imposed by the current source Iref3.

Thus, the current source Iref3 may be configured for generating acurrent of low intensity, for example, substantially equal to 1 μA,allowing the invention to be adapted to systems with low powerconsumption.

Furthermore, the range of voltages on the bit line BL is limited by thethreshold voltage of the transistor MN1 to the minimum and by thevoltage applied to the source line SL to the maximum, also allowing theinvention to be used in systems with low power consumption.

It turns out that, during the read operation, no current leakage due toa ground potential on a drain or a source of a transistor of the memorycells is able to interfere with the read current of the bit line.

This advantageous result comes notably from the introduction of thesubstrate effect (in other words the low level of the electrodes of thetransistors is higher than ground) into all the possible passages of thecurrent leaks.

It then becomes possible to reduce the lengths of the state andselection transistors of the memory cells, and also the space betweentwo neighbouring bit lines of a memory plane, without howevercompromising the functionality of the memory owing to excessive currentleaks.

By way of illustrative example, the present invention allows the surfaceareas of the memory cells currently used to be reduced by close to 50%.

Furthermore, the invention is not limited to the embodiment previouslydescribed but encompasses all its variants. For example, the outputstage could comprise a differential amplifier, and the pre-chargevoltage could be formed and maintained by any other means.

What is claimed is:
 1. A method for reading a memory cell of a memoryplane of a memory of the erasable electrically-programmable ROM type,the method comprising: selecting a word line and a bit line to which thememory cell belongs; pre-charging the bit line at a pre-charge voltage;performing a read operation to read information from the memory cell viaa read amplifier that has an input coupled to the pre-charged bit line;and during the read operation, applying a source voltage higher than thepre-charge voltage to a source of a floating-gate transistor of thememory cell so that a read current flows from the memory cell towardsthe input of the read amplifier and then flows through a programmedcell.
 2. The method according to claim 1, wherein the memory cellcomprises a selection transistor that has a source connected to a drainof the floating-gate transistor, a gate connected to the word line, anda drain connected to the input of the read amplifier via an auxiliarytransistor that is configured to select the bit line, wherein bodies ofthe selection transistor and of the floating-gate transistor areconnected to ground.
 3. The method according to claim 1, furthercomprising reading an erased cell of the memory plane, a voltage presentat the input of the read amplifier being prevented from falling belowthe pre-charge voltage during the reading.
 4. The method according toclaim 3, wherein the pre-charge voltage is equal to a threshold voltageof an MOS transistor, the source voltage being higher than the thresholdvoltage of an MOS transistor.
 5. A memory device of the erasableelectrically-programmable ROM type, the memory device comprising: amemory plane of memory cells; a read circuit comprising a read amplifierthat has an input configured to be pre-charged at a pre-charge voltage;and a controller configured to select a word line and a bit line towhich a cell belongs, so as to read information from the memory cell viathe read amplifier, which is coupled to the selected bit line, whereinthe controller is configured to apply a source voltage higher than thepre-charge voltage to a source of a floating-gate transistor of thememory cell so that a read current flows from the memory cell towardsthe input of the read amplifier and then flows through a programmedcell.
 6. The memory device according to claim 5, wherein the memory cellfurther comprises a selection transistor having a source coupled to adrain of the floating-gate transistor, a gate coupled to the selectedword line, and a drain coupled to the input of the read amplifier via anauxiliary transistor configured for selecting the bit line.
 7. Thememory device according to claim 6, wherein a body of the selectiontransistor and a body of the floating-gate transistor are connected toground.
 8. The memory device according to claim 5, wherein the readamplifier is configured to prevent a voltage present at the input of theread amplifier from falling below the pre-charge voltage when reading anerased cell.
 9. The memory device according to claim 8, wherein the readamplifier is configured so that the pre-charge voltage is equal to athreshold voltage of an MOS transistor.
 10. The memory device accordingto claim 5, wherein the read amplifier comprises a feedback loopcontaining a common source configuration of a first MOS transistor incommon source configuration, a drain of the first MOS transistor beingconnected to a gate of a second MOS transistor in source followerconfiguration and a source of the second MOS transistor being fed backonto a gate of the first MOS transistor and connected to the input ofthe read amplifier.
 11. The memory device according to claim 10, whereinthe feedback loop prevents a voltage present at the input of the readamplifier from falling below the pre-charge voltage.
 12. The memorydevice according to claim 11, wherein the pre-charged voltage is equalto a threshold voltage of the first MOS transistor.
 13. The memorydevice according to claim 10, wherein the read amplifier comprises acurrent source configured to impose a current to ground on the feedbackloop and bit-line.
 14. A read amplifier for use in a memory device thatincludes a plurality of memory cells of the erasableelectrically-programmable ROM type, the read amplifier comprising: afirst current generator; a first transistor having a gate coupled to aninput node of the read amplifier and also having a current path coupledbetween the first current generator and a ground node; a secondtransistor having a gate coupled to a node between the first transistorand the first current generator and also having a current path coupledbetween a reference voltage node and the input node of the readamplifier; a third transistor having a current path coupled between thegate of the second transistor and the ground node; a second currentgenerator; a fourth transistor having a gate the gate of the secondtransistor and also having a current path coupled between the secondcurrent generator and the ground node; a first inverter with an inputcoupled to a node between the fourth transistor and the second currentgenerator; and a fifth transistor having a current path coupled betweenthe reference voltage node and the input of the first inverter.
 15. Theread amplifier according to claim 14, further comprising a secondinverter with an input coupled to an output of the first inverter. 16.The read amplifier according to claim 14, wherein the first, second,third and fourth transistors comprise n-type MOS transistors and whereinthe fifth transistor comprises a p-type MOS transistor.
 17. The readamplifier according to claim 14, further comprising a third currentgenerator coupled between the input node of the read amplifier and theground node.
 18. A memory device comprising: the read amplifier of claim14; and a memory plane comprising a column of memory cells coupled to abit line, the bit line being coupled to the input node of the readamplifier through a select transistor.
 19. The memory device accordingto claim 18, wherein each memory cell comprises a floating gatetransistor coupled in series with a selection transistor.
 20. The memorydevice according to claim 18, further comprising a pre-charge circuitcoupled to the bit line.
 21. The memory device according to claim 18,further comprising a controller with an output coupled to a gate of theselection transistor.
 22. The memory device according to claim 21,wherein the controller is configured to pre-charge the input node of theread amplifier at a pre-charge voltage, to select the bit line and aword line associated with one of the memory cells to be read via theread amplifier, wherein the controller is configured to apply a sourcevoltage higher than the pre-charge voltage to a source of afloating-gate transistor of the one of the memory cells so that a readcurrent flows from the one of the memory cells towards the input node ofthe read amplifier and then flows through a programmed cell.